1. Technical Field
The present invention relates to signal generators, and more particularly, to a signal generating circuit for generating a plurality of delayed tap signals.
2. Description
In an output driver of a memory device divided into a plurality of segments, the slew rate of an output signal output to the output driver is adjusted by turning on or turning off each segment at a predetermined interval.
When the operating frequency of a memory device is low, the adjustment of the slew rate of an output signal is not so important. However, as the operating frequency of a memory device becomes higher, an apparatus for adjusting the slew rate of an output signal is required.
To adjust the slew rate of an output signal, which is output to an output driver divided into predetermined segments, a plurality of signals having respective constant delays are needed. Such signals are normally called “delayed tap signals.” The delayed tap signals having the respective constant delays are synthesized so as to adjust the slew rate of the output signal output from an output driver.
For example, when four tap signals are used to adjust the slew rate, if delay differences between the tap signals are small, the four tap signals are synthesized to obtain an output signal having a high slew rate. Inversely, if delay differences between the tap signals are large, the four signals are synthesized to obtain an output signal having a low slew rate.
Delayed tap signals may be produced by various methods. For instance, a plurality of inverters having identical delays can be used. That is, outputs of the respective inverters are used as the delayed tap signals. An interval between the tap signals is determined by the delay of an inverter. Also, a plurality of inverters and a plurality of variable delay cells may be utilized to control an interval between output delayed tap signals.
FIG. 1 is a circuit diagram of a conventional delayed tap signal generating circuit using a plurality of inverters. A tap signal generating circuit 100 of FIG. 1 includes a plurality of inverters 101, 102, 103, 104, 105, 106, 107, and 108, which are connected in series.
The tap signal generating circuit 100 delays an input clock signal CLK_IN by the delays of a series of inverters and produces tap signals TAP1, TAP2, TAP3, and TAP4 at each output of a pair of series-connected inverters. That is, the delay difference between two of the tap signals depends on the delay of an inverter.
For example, when the delay of each of the inverters 101, 102, . . . , and 108 as illustrated in FIG. 1 is 50 ps, each delay difference between the tap signals TAP1, TAP2, TAP3, and TAP4 is 100 ps. That is, the delay difference between the tap signals TAP1 and TAP2 is 100 ps, the delay difference between the tap signals TAP2 and TAP3 is 100 ps, and the delay difference between the tap signals TAP3 and TAP4 is 100 ps.
However, in the tap signal generating circuit 100 of FIG. 1, the delay difference between the delayed tap signals is determined by the delay of an inverter. For this reason, a system requiring fine delayed tap signals, in which the required delay difference between tap signals is less than the delay of one inverter, cannot use the tap signal generating circuit 100 of FIG. 1.
Namely, when the delay difference (interval) between delayed tap signals is required to be 20 ps and the delay of one inverter is 50 ps, the tap signal generating circuit of FIG. 1 cannot generate the required delayed tap signals.
The present invention provides a circuit and method of generating delayed tap signals which can meet the required fine delay difference between delayed tap signals.
In accordance with an aspect of the present invention, there is provided a delayed tap signal generating circuit, comprising a first tap signal generating circuit for receiving a first clock signal and a second clock signal, which have the same frequency and a predetermined phase difference, and generating a first tap signal in response to the first and second clock signals and a predetermined offset information, wherein the first tap signal is delayed by a first delay corresponding to the offset information based on the first clock signal; and a second tap signal generating circuit for receiving the first and second clock signals, and generating a second tap signal in response to the first and second clock signals and the offset information, wherein the second tap signal is delayed by the first delay and a second delay added by the first delay based on the first clock signal. The first and second tap signals are generated by interpolating the first and second clock signals in response to the offset information.
Preferably, the first tap generating circuit includes a first N-bit adder for receiving the offset information, converting the offset information into an N-bit digital signal, adding a predetermined default signal to the N-bit digital signal, and outputting the result; a first digital/analog converting circuit for receiving the output signal of the first N-bit adder, converting the output signal of the first N-bit adder into an analog signal and outputting the analog signal; and a first interpolating circuit for receiving the first and second clock signals, interpolating the first and second clock signals in response to the output signal of the digital/analog converting circuit, and outputting the first tap signal.
Preferably, the second tap generating circuit includes a second N-bit adder for receiving the offset information, converting the offset information into the N-bit digital signal, adding the output signal of the first N-bit adder to the N-bit digital signal; a second digital/analog converting circuit for receiving the output signal of the second N-bit adder, converting the output signal of the second N-bit adder into an analog signal, and outputting the analog signal; and a second interpolating circuit for receiving the first and second clock signals, interpolating the first and second clock signals in response to the output signal of the digital/analog converting circuit, and outputting the second tap signal.
In accordance with another aspect of the present invention, there is provided a delayed tap signal generating circuit, comprising a second tap signal generating circuit for generating a second tap signal in response to a first clock signal, a second clock signal, and a predetermined offset information, wherein the second tap signal is delayed by a first delay corresponding to the offset information based on a first tap signal; and a third tap signal generating circuit for receiving the first and second clock signals and generating a third tap signal in response to the first and second clock signals and the offset information, wherein the third tap signal is delayed by the first delay and a second delay added by the first delay based on the first tap signal; and a fourth tap generating circuit for receiving the first and second clock signals and generating a fourth tap signal in response to the first and second clock signals and the offset information, wherein the fourth tap signal is delayed by the second delay and a third delay added by the first delay based on the third tap signal. The first tap signal is the first clock signal, and the second, third, and fourth tap signals are generated by interpolating the first and second clock signals in response to the offset information.
Preferably, the second tap signal generating circuit includes a first N-bit adder for receiving the offset information, converting the offset information into an N-bit digital signal, adding a predetermined default signal to the N-bit digital signal, and outputting the result; a first digital/analog converting circuit for receiving the output signal of the first N-bit adder, converting the output signal of the first N-bit adder into an analog signal, and outputting the analog signal; and a first interpolating circuit for receiving the first and second clock signals, interpolating the first and second clock signals in response to the output signal of the digital/analog converting circuit, and outputting the first tap signal.
In accordance with yet another aspect of the present invention, there is provided a method of generating delayed tap signals, comprising (a) receiving a first clock signal and a second clock signal, which have the same frequency and a predetermined phase difference, and generating a first tap signal in response to the first and second clock signals and a predetermined offset information, wherein the first tap signal is delayed by a first delay corresponding to the offset information based on the first clock signal; (b) receiving the first and second clock signals and generating a second tap signal in response to the first and second clock signals and the offset information, wherein the second tap signal is delayed by the first delay and a second delay added by the first delay based on the first clock signal. Here, the first and second tap signals are generated by interpolating the first and second clock signals in response to the offset information.
In accordance with further another aspect of the present invention, there is provided a method of generating delayed tap signals, comprising (a) generating a second tap signal in response to the first and second clock signals and a predetermined offset information, wherein the second tap signal is delayed by a first delay corresponding to the offset information based on a first tap signal; (b) generating a third tap signal in response to the first and second clock signals and the offset information, wherein the third tap signal is delayed by the first delay and a second delay added by the first delay based on the first tap signal; and (c) generating a fourth tap signal in response to the first and second clock signals and the offset information, wherein the fourth tap signal is delayed by the second delay and a third delay added by the first delay based on the third tap signal. Here, the first tap signal is the first clock signal, and the second, third, and fourth signals are generated by interpolating the first and second clock signals in response to the offset information.